Conventional computing systems (e.g., personal computers, cellular phones, personal digital assistants, media players and digital cameras) shave controlling features. Power control is used to reduce the dynamic and static power consumption of a system to increase the battery life and to reduce energy costs of the system, which is particularly valuable in mobile devices. Dynamic power is consumed by all components of a system during state switching of internal electronic circuits (i.e. while the device is in active operation), while static power is consumed due to the leakage currents of electronic devices.
In a conventional technique, “sleep” transistors are used to cut off power supplies to logic blocks of an electronic device when the device is in a low-power state. In some conventional solutions, a memory is provided with a reduced-supply voltage in a sleep mode.
FIG. 1 illustrates a conventional power control circuit 100, which includes a memory block 110 coupled to a PMOS (P-channel Metal Oxide Semiconductor) transistor 120. The power control circuit 100 is coupled between a supply voltage “vpwr” and a grounded terminal “vgnd.” The PMOS transistor 120 is coupled between a global power supply voltage “vpwr” and local power supply voltage “vpwr local.” A gate terminal (not shown in the figure) of the PMOS transistor 120 is coupled to a control signal “sleep”, which when enabled causes the memory block 110 to go into a sleep/power reduction mode. However, the conventional power control circuit 100 does not provide low power, power cut off and data retention features at the same time. This means that if the device enters a low power mode, the data is lost (i.e. not retained).